The present invention generally relates to semiconductor devices and more particularly to the fabrication process of a semiconductor device that has a contact structure contacting with a diffusion region or gate electrode formed on a semiconductor substrate.
In the art of MOS semiconductor integrated circuit devices, increase of integration density and decrease of device size are steadily in progress for the purpose of achieving higher operational speed, diversified functions, larger storage capacities and lower power consumption. Today, there emerged semiconductor devices that have a gate length of less than 100 nm. With such ultra-miniaturized semiconductor devices, there arise various problems to be solved, and innovation of technology has become inevitable.
Patent Reference 1 Japanese Laid-Open Patent Application 8-45878 official gazette
Patent Reference 2 Japanese Laid-Open Patent Application 11-214650 official gazette